Serial digital data is frequently transmitted using a self-clocking encoding. The basic idea behind these self-clocking codes is to guarantee that a certain minimum number of digital "events" (pulses or transitions in level) occur within the digital waveform. These "guaranteed" events can then be used to establish and reconstruct frequency and phase of the clocking signals which were used to encode and transmit the data.
"Double frequency modulation" encoding is the simplest of the self-clocked encodings. It is characterized by a guarantee that at least one, but no more than two digital events occur per bit cell in the digital waveform. A bit cell is that portion of the waveform which is generated by one cycle of the basic digital clock and contains a single binary "0" or binary "1". The presence or absence of the second (non-guaranteed) event depends upon the data being encoded.
Double frequency modulation (DFM) is referred to in the prior art as biphase-mark, frequency modulation (FM), diphase, and frequency shift code (FSC).
A DFM encoded waveform contains pulses of two widths, long and short. A long pulse is twice the width of a short pulse. Pulse width is defined as the time between two transitions or edges. DFM waveforms alternate between positive and negative pulses.
The DFM encoding algorithm is quite simple. A sequence of two short adjacent pulses of opposite polarity represents a logical "1" (or "mark"), while a long pulse of either polarity represents a logical "0" (or "space"). DFM encoding may also be characteirzed by the edges or transitions in the encoded waveform. A transition occurs at the start of every bit cell. A "1" has an additional transition in the middle of the bit cell. A "0" does not have any mid-cell transition. Another way of looking at the encoding is that a "0" is encoded as a low frequency element, while a "1" is encoded as a high frequency element; hence the name double frequency modulation.
Recovering data and clock information from a DFM waveform depends on the ability to recognize the guaranteed transitions and to synchronize some timing circuit with these recognized guaranteed transitions. The output of the timing circuit can then be used, along with some additional logic, to extract data from the waveform. In the prior art, various timing circuits have been used for this purpose. Two commonly used techniques are briefly discussed below.
In the prior art technique, monostable multivibrators triggered by the guaranteed transitions define a "window" during an interval when a non-guaranteed transition may occur. The pulses produced by the monostables are then used to extract data from the waveform. Technique 1 has the advantage of simplicity, but suffers from wide variations in timing common with monostables. Further, technique 1 is quite susceptible to spurious operation induced by noise in the incoming waveform and is limited to usage with relatively low frequency signals.
In the second prior art technique, a variable frequency oscillator is synchronized to the incoming frequency by means of a phase-locked loop. The output of the oscillator is then used to extract data from the incoming waveform. Technique 2 eliminates the timing tolerance problem associated with technique 1 and is much less prone to noise induced failure. However, technique 2 is substantially more complex than technique 1. When working at high data rates (on the order of 100 Mb/s or higher) there can be problems obtaining cost effective phase-locked loops that have the proper parameters. In addition, a continuous bit stream of approximately forty or more bits is needed to lock the phase-locked loop onto the desired frequency.
In certain applications where units containing circuits exemplified by techniques 1 to 2 are placed in series, such as in a ring network, the clocking signals derived from the incoming waveform are used to construct an outgoing waveform for transmission to the next unit downline. In such a configuration, "jitter" (viz., timing uncertainty) in the output waveform must be minimized since the jitter may cascade and be amplified by passage through several units in series. Phase-locked loops, such as those of technique 2, always exhibit frequency jitter. The amount of jitter is traded off against capture time (time to go from initial "unlocked" state to "locked") and lock range (input frequency range within which the phase-locked loop will eventually enter the locked condition). Since less jitter means less tracking ability and hence greater sensitivity to component value tolerances, technique 2 may be unsuitable for applications in which many units, each containing the extraction circuit, are cascaded in series. Using technique 1 it is possible to design a circuit which exhibits no jitter beyond that present in the incoming waveform, but one that suffers from the aforementioned drawbacks.
Previous efforts have been made to overcome the above discussed drawbacks of the prior art. For example, in U.S. Pat. Nos. 4,313,206 and 4,320,525 both of which are assigned to the same assignee as the present invention, circuits are disclosed for reconstructing the timing information encoded in a double frequency transition event waveform. However, neither of these techniques provides for recovering the encoded data information. In addition, these prior art techniques are designed to handle waveforms having a frequency of 1 MHz. In contrast, some present and many planned communications systems must be capable of operating at speeds exceeding 100 MHz.